The present invention relates generally to semiconductor memory devices and, more specifically, to a signal delay control circuit for use in a memory device to improve the delay difference of signals resulting from components or circuits spaced a different distance from a transmission device such as a control circuit.
In a general semiconductor memory device, signal delays proportional to the propagation distances occur when a signal is transmitted from a specific position to circuit elements or devices at various positions. A typical configuration of a semiconductor memory device wherein signal delays are dependent on propagation distance of signals is illustrated in FIG. 1. As shown in FIG. 1, a control signal such as a clock signal is generated from a control signal generator 1 which is positioned at the center area of a chip. An output pin DQm of a data pin array is located relatively near to the control signal generator 1 while an output pin DQ1 is relatively far away from the control signal generator 1. When data bits are output from the output pins DQ1 to DQm in response to the clock signal generated from the control signal generator 1, a data bit from DQm outputs earlier than that from DQ1.
Also, an address pin A1 is relatively near to the control signal generator 1 while an address pin An is relatively far away from the control signal generator 1. Thus, when address bits are input into the chip through the address pins A1 to An in response to the clock signal generated from the control signal generator 1, the input of the address bit through address pin A1 is faster than that through address address pin An.
Referring to FIG. 2, a clock signal A is applied to a data input/output circuit which is near to the control signal generator 1 while a clock signal B is applied to another data input/output circuit which is far away from the control signal generator 1. The slopes at the rising edges of the clock signals A and B are different from each other.
Briefly, a delay difference between pins based on input positions of the clock signal, is usually more than 1 ns (nanosecond) in a semiconductor memory chip having a chip size of 1 cm by 2 cm and having data output pins disposed at the side region stretching over 1 cm.
As aforementioned, a device which outputs data signals synchronized with the clock signal (e.g., SDRAM (synchronous DRAM)), has various output times due to the difference of the slope of the rising edge (or a rising time of the clock signal) in accordance with the distance between the control signal generator 1 and the data input/output circuits. A data output circuit adjacent to the control signal generator 1 outputs a data bit quickly, while another data output circuit located away from the control signal generator 1 outputs a data bit slowly. Such a difference in data output time causes a valid data window to be narrower and acts as an obstacle for high frequency operation.
In order to minimize the difference in data output time, transmission lines of clock signals are conventionally arranged with a tree shape in order to unify the distance between a clock driver (e.g., the control signal generator 1) and data output buffers. However, there is a problem in the conventional approach in that an excessive increase of circuit area is required for adjusting minute delay times.
In accordance with an aspect of the invention, a signal delay control circuit is provided for use in a semiconductor memory device. The signal delay control circuit comprises a first reference voltage generating unit for generating a first reference voltage; a second reference voltage generating unit for generating a second reference voltage that is lower than the first reference voltage; a control signal generating unit for generating a clock signal to drive an operation of internal circuits; and an impedance circuit in circuit with the first and second reference voltage generating units for generating a plurality of reference voltages to be applied to respective ones of the internal circuits. Each of the reference voltages is set in accordance with a distance between the control signal generating unit and the respective one of the internal circuits.
In accordance with another aspect of the invention, a signal delay control circuit is provided for use in a semiconductor memory device. The signal delay control circuit comprises: a first reference voltage generating unit for generating a first reference voltage; a second reference voltage generating unit for generating a second reference voltage that is lower than the first reference voltage; a control signal generating unit for generating a clock signal to control input and output operations for data bits; a resistive circuit in circuit with the first and second reference voltage generating units for generating a plurality of reference voltages; and a plurality of data output units for outputting data bits from the semiconductor memory device in response to a respective one of the reference voltages. Each of the reference voltages corresponds to a distance between the control signal generating unit and a respective one of the data output units.
In accordance with another aspect of the invention, a signal delay control circuit is provided for use in a semiconductor memory device. The signal delay control circuit comprises: a first reference voltage generating unit for generating a first reference voltage; a second reference voltage generating unit for generating a second reference voltage that is lower than the first reference voltage; a control signal generating unit for generating a clock signal to control input operations for address bits; a resistive circuit in circuit with the first and second reference voltage generating units for generating a plurality of reference voltages; and a plurality of address input circuits for controlling strobe operations in response to a respective one of the reference voltages. Each of the reference voltages corresponds to a distance between the control signal generating unit and a respective one of the address input circuits.
In accordance with still another aspect of the invention, a signal delay control circuit is provided for use in a semiconductor memory device. The signal delay control circuit comprises: a first reference voltage generating unit for generating a first reference voltage; a second reference voltage generating unit for generating a second reference voltage that is lower than the first reference voltage; a control signal generating unit for generating a clock signal to control operations of sense amplifiers; a resistive circuit in circuit with the first and second reference voltage generating units for generating a plurality of reference voltages; and a plurality of sense amplifier drive circuits for controlling operations of sense amplifiers in response to a respective one of the reference voltages. Each of the reference voltages corresponds to a distance between the control signal generating unit and a respective one of the address input circuits.